本文相关DataSheet：
许多应用程序需要一个取样电路的输出对于一个输入信号的各个采样点是反向的。一个简单的办法，是一个连续不断的一个共同非反向采样-保持放大器和一个反相放大器。一个典型的反相放大器是一个拥有从两个电阻的得到的电压反馈的运算放大器。这些电阻的值必须足够的高来减少总功率P=2V2/R的损耗，这些电阻值和输出电压的平方成正比。这些电阻的值也应该尽可能低的来保持运算放大器的带宽。
任何寄生电容（C2在下面的公式）和反馈电阻R2并联在变极器的转移功能里担当了一极。这一极导致反相放大器的一个附加的增益频率击穿特性，击穿频率的值为f2=(1/2π)×(1/R<?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />2C2)，f2>fT来保留尽可能宽的带宽，fT为运算放大器的转换频率--换句话说，这个频率为运算放大器的开环增益下降到整体增益时的频率。
双运算放大器设备AD8592拥有一个高品质的断路功能。反向取样保持电路在图一里没有使用任何的外部电阻。因此，在该电路的保持状态下，没有能量消耗在外部的无源器件。所有的运算放大器都担当着电压输出器的职责。这种情况引起负极电压–VS出现在电压跟随器B2的输入端。电压跟随器B2在取样命令的初期轮流看管 C2 电容器和电压–VS。跟随器A3作为一个阻抗转换器来提供供给。
AD8592的记录表不会直接详细说明电压跟随器输出端的泄漏电流，然而，你可以把他估计到低于10 Pa。电容器C1和C2因此可以有很小的值，另外，运算放大器的高输出电流250 mA可以更进一步的给电容器C1和C2快速的充电服务。
电压跟随器B3作为一个延迟线与一个AND门和一个NOR门协作产生两个半互补的逻辑控制信号（图２）。这两个信号QS和
在进入到一个活动的高电平前一段十分长的时间内被保持在一个停止的低电平。提供了一个先离后合接点的操作。输入电压被追踪在电容C1和高电平的时候，在这个电压的最后一个值的时候，的高－低的转换就是一个取样。在QS低－高的转换的瞬间的取样和一个负信号一起出现在电容器C2和后来的输出里面。
本文相关DataSheet：
Many applications require a sampling circuit whose output is inverted with regard to the respective sample of an input signal. A simple approach is a cascade of a common noninverting sample-and-hold amplifier and an inverting amplifier. A classic inverting amplifier is an op amp with voltage feedback from two resistors. The values of these resistors, which are usually equal, should be high enough to decrease the total power loss of P=2V2/R, which is proportional to the square of the output voltage. The values of these resistors should be as low as possible to preserve the bandwidth of the op amp.
Any parasitic capacitance (C2 in the following equation) parallel to feedback resistor R2 forms a pole in the transfer function of the inverter. This pole results in an additional breakdown of the gain-frequency characteristic of the inverting amplifier, with the value of breakdown frequency of f2=(1/2π)×(1/R2C2)，To retain the widest possible bandwidth, f2>fT, where fT is the transition frequency of the op amp—in other words, the frequency at which the open-loop gain of the op amp drops to unity.
The Analog Devices’ AD8592 dual op amps, which have a high-quality shutdown function, allow you to use a different approach (Reference 1). The inverting sample-and-hold circuit in Figure 1 uses no external resistors. Thus, no power dissipates at external passive devices in the hold state of the circuit. All op amps act as voltage followers. In the hold state, followers B1 and A2are enabled; thus, the B lead of the C1 capacitor, Pin 1 of IC2, is grounded through the output of A2, and the input voltage, VIN, gets followed at the A lead of the C1, Pin 9 of IC1. Upon the sampling command, Q is high, and, at this time, the A lead of C1 gets grounded through the output of the A1 follower. This scenario causes a negative voltage of –VS to appear at the input of the B2voltage follower, which in turn charges the C2 capacitor to the voltage of –VS at the beginning of the sampling command. Voltage follower A3 serves as an impedance converter.
The AD8592’s data sheet does not directly specify the leakage current at the output of the voltage follower; however, you can estimate it as being lower than 10 pA. Capacitors C1 and C2 thus can have unusually low values. On the other hand, the op amps’ high output current of 250 mA contributes further to the fast charging of capacitors C1 and C2.
The B3 voltage follower serves as a delay line, which, in conjunction with one AND gate and one NOR gate, generates two semicomplementary logic-control signals (Figure 2). Both of these signals, QS and 
are thus kept at an inactive low level for a sufficiently long time, before moving to an active high level, providing a break-before-make operation. The input voltage gets tracked at the C1 capacitor with high, and the last value of this voltage, at the high-to-low transition of is a sample. The sample, at the instant of the low-to-high transition of QS, appears with a negative sign at capacitor C2 and subsequently at the output.
英文出处：
