The key word is high speed serially interlocks, RocketIO, the light interlocks, FPGA
Design And Application In The Optical Interconnection Of High Speed Serial IO Based On Virtex - II Pro

FAN Yong WANG Jingcun
University of Science and Technology Beijing Information Engineering Institute
NO.30, Xueyuan Road, Haidian Zone, Beijing P.R.China 100,083
Fanyong-2001@sohu.com
Wjc9804@163.com

Abstract At present, the data transmitting rate of the processor has already been higher than the transmitting rate of the data bus. Increasing the bandwidth of parallel bus can enhance throughput among chips and backboards. But enhancing bandwidth and transmitting rate increase difficulties of PCB routing and signal delay or skew. The technology of high-speed serial interconnection is an efficient way for enhancing bandwidth of data. In this paper, This paper introduce operation method and the application in the optical interconnection of RocketIO which is embedded in Virtex- II Pro FPGA in Xilinx Corp to solve problem of high-speed serial interconnection..

Keywords High-speed serial interconnection, RocketIO, Optical interconnection, FPGA
Introduction
Is day by day popular along with the Internet application and the rapid development, the logarithm according to the transmission demand sharp growth. In addition, digital television and colored picture even need higher band width. The data exchange bottleneck exists to the system interlocks a level, namely in system mutual correspondence as well as with exterior other system communication between different component speeds. This needs one kind of new system to interlock the technology to come to transform the CPU performance into the system performance.
Generally speaking, the increase parallel main line width may enhance between the chip and the chip, 背板and 背板the between data volume of goods handled. But the main line number increases and the transmission speed speeds up can increase suddenly the PCB wiring difficulty and the signal extends now and then displaces, thus makes to enhance the main line data turnover rate request faced with a limit.
High speed serial interlocks the technology because carries on the clock and the data merge the transmission, thus has overcome the clock and the data vibration question, can enormously enhance the transmission speed, reduces the IC periphery pin number, reduces the power loss and obtains the better signal integrity. [ 1> component has provided IP in Xilinx Corporation's Virtex- II Pro in the FPGA which uses in to realize high speed serial interlocks nucleus -RocketIO. This article quite in detail will describe this IP nucleus structure, the principle and the question which will need to pay attention in the application, simultaneously introduced its hardware test method and will interlock the aspect application in the high speed light.
1 RocketIO structure and principle
Is high speed serially in the support interlocks in technology transmission mode FPGA, affects the transmission speed the key aspect to have following several points:
(1) serial input - parallel output transformation structure and parallel input - serial output switch structure, also is called the string (Serializer) to reconcile the string (Deserializer) the structure
(2) the clock and the signal restore the electric circuit (Clock & Data Recovery), it is the guarantee high speed captures one of data key aspects.
(3) the system clock management and the PLL electric circuit, it solves the board level and the FPGA interior clock synchronization question, displaces slightly between the data stream displacement and the channel.
Under introduced how RocketIO will be solves these problems from the principle and the structure.
1.1 RocketIO structure
RocketIO is has the clock data to restore the function the entire duplex serial transceiver, but effectively implements each channel band width to achieve 3.125Gb/s the different agreement design, and may tie up using the channel surely satisfies the logarithm which each kind of application unceasingly grows according to the speed and the position wide request. Its structure like chart 1 shows [ 2>:

Chart 1 RocketIO structure diagram

The RocketIO module constitutes by the below two parts:
(1) physics arranges the numeral level (PCS, Physical Coding Sublayer)
This module provides with the FPGA logic in the digital interface, its interior includes: The circulation redundant code verifies CRC, 8B/10B arranges the decoding advanced, first leaves buffer FIFO, receives in the channel to have the elastic buffer, the channel ties up decides revises the processor with the clock.
(2) the physical medium turns on the level (PMA, Physical Media Sublayer)
This module provides with exterior media simulation connection, its interior including 20 time of clocks frequency multipliers, the transmitting end clock production, transmits the buffer, the string, the receiving end clock restores the electric circuit, receives the buffer, Xie Chuanqi, the invariable speed (50 ~ 156.25MHz) the entire duplex transceiver, the programmable five levels of differences output scope (suspending rate) controls, the programmable four levels of outputs 预加�?model, uses in to improve the output signal the integrity.
1.2 RocketIO principle
As FPGA the internal IP nucleus, RocketIO has provided 9 kind of signals to the user, completes the data through them the transmission, the data receive, the data transmission condition monitor as well as the channel ties up decides the function, they respectively are the data transmission signal, the data transmission condition signal, the transmission mouth control signal, the data receive signal, the data receive control signal, the data receive condition signal, the channel tie up decide the signal, the transceiver control signal, the clock signal.
Under unifies RocketIO the structure diagram to explain its principle of work.
RocketIO may receive 3.2/16/8 million data through the attribute establishment and transform it the serial bit class to transmit.
To the parallel data which enters may choose whether joins the CRC verification code as well as the verification scope. If chooses joins the verification code, in the transmitting end, the transmitter counts Baotou (SOP) and a package of tail (EOP) the between data, and forms 4 byte CRC code. The transmitter inserts this CRC code to the data packet finally (before the EOP symbol). Therefore, needs in transmits in the buffer to remain has 4 bytes spaces. Moreover, has the special-purpose output signal in the receiving end to express CRC verifies whether makes a mistake. The RocketIO CRC verification only can realize in the single channel, cannot complete the byte which analyzes to the multichannel in to carry on the CRC verification and the statistics.
After the CRC statistics verification data may choose whether carries on the 8B/10B code. This kind of code pattern refers to 8 data positions transforms into not continuously 5 above "1" or "0" 10 bit codes, by obtains better direct current (DC) the balanced state. The 8B/10B code may have 256 kind of combinations and two kind of data types: (1) the data code group (sign is D), uses in the data transmission. (2) the specific control code group (sign is K), uses in the control sequence transmission.
Enters TX FIFO after the 8B/10B encoded data, after this is a 4×20 position buffer (20 extends the =2 byte to pass through 8B/10B code width), its main function is adjusts between the clock 相位�?
The reference clock produces 20 frequency multiplications clocks through the monolithic integrated PLL electric circuit, under its function, the parallel data is transformed outputs for the serial data by TXP and the TXN difference port. In order to make the test to be convenient, may output through internal closed loop the difference signal directly to give Xie Chuanqi. Restores the electric circuit in the clock/data under the function, solves the clock from the receive serial data stream the frequency and the phase, restores its 20 frequency divisions clocks achievement the clock. In restores under the clock function to have 10 bit parallel data from Xie Chuanqi to use in the 8B/10B decoding input, after the decoding data enters the receive elastic buffer.
After the receive elastic buffer (RX Elastic Buffer) is a 64×13 position buffer (13 widths = 1 byte 8B/10B decoding width + 3 status byte). This buffer by restores the clock achievement to write the clock, but reads the clock by to write the clock to produce and the actuation, these two clocks phase relation is cannot be known in advance, because restores the clock to need (Digitial Clock Manager) or the BUFG production reads the clock after DCM. Therefore needs to have the clock in the receive elastic buffer to revise avoids its overflow. The clock revises the basic principle is in the transmitting end, after the data has transmitted the certain byte or several data packets, through inserts and transmits some specific bytes (revision character); In receiving end, after will receive these characters to be able automatically to discard.
Moreover, RocketIO provided the channel to tie up decides (Channel Bonding) the function. Because RocketIO each channel most greatly only can provide 3.125Gb/s the data output rate, if needs to obtain the higher data bandwidth, must combine several channels, this is the channel ties up decides. For example, transmits 16 data by the 125M clock, after considers the 8B/10B code, actual transmission band width for 20b×125MHz=2.5Gb/s. This only can in a RocketIO realization. If by similar band width transmission data time must use two RocketIO module the way realization which to the channel ties up decides.
Carries on the simulation to the RocketIO module to need to use SmartModels, may carry on the simulation through it to the RocketIO module actual function, the concrete detail may refer to XILINX solution Solution Record 15,501 [ 2>.

2 RocketIO hardware tests several methods
When the RocketIO module design completes and through the simulation confirmation, needs to confirm RocketIO from the hardware the working condition, under, unifies us to use RocketIO the experience, introduces two quite practical hardware tests method.
2.1 uses integrations logic analysis tool
Xilinx promoted using the high performance logic component characteristic has set to FPGA the internal logical analyzer - ChipScope integration logic analysis tool. This analysis tool and the ISE6 project browser integration is closer, but conveniently the choice and the insertion confirmation core, defines the signal test point, simultaneously provides the real-time debugging plan ability for the overall design flow.
Its main function is through the JTAG programming connection, on-line, real-time reads out the FPGA interior the signal. Its basic principle is uses in FPGA the use block memory, triggers the condition according to the user hypothesis, real-time preserves the signal in these memories, then delivers the computer through the JATG connection biography, and demonstrated through computer user contact surface GUI gathers succession profile. Its design flow like chart 2 shows:

Chart 2 ChipScope tool design flow
Through the ChipScope integration logic analysis tool, may downloads when the RocketIO module to the chip conveniently observe the change of state and the data transmission situation.
2.2 uses computers string mouth tectonic analysis tool
ChipScope the IP nucleus joins the original design, can take the chip part of resources, to the design synthesis, the layout wiring has the certain influence. In to the succession request sensitive design in, the extra resources expenses can have the indefinite influence in particular. In view of the fact that this kind of situation, we refer to ChipScope the basic principle, simply used the computer string mouth structure one kind, has been effective, the resources expenses smaller analysis tool.
Under, take tests the RocketIO data transmission as the example to introduce this method, like chart 3 shows.

Chart 3 the use string mouth observes the RocketIO data transmission schematic drawing

The supposition needs to transmit 32 bit parallel data by the FPGA interior production, transform 32 bit parallel data again through the RocketIO module production serial data through the internal closed loop, for observation data in RocketIO module internal conversion is whether correct, will transform after the parallel data to put in double port RAM, when the data transmission finished, again will transmit orally through the FPGA interior structure string mouth controller the data through the string the computer to perform to analyze.
This method structure string mouth controller only takes the very small chip resources, the double port RAM size may establish by the user. Moreover, this method also may take lowly carries FPGA or the CPLD development method, because these chips do not support the integration logic analysis tool.
3 RocketIO interlocks in the connection card application in the high speed light
We apply RocketIO to the high speed light interlock in the connection card design, through the DDR memory interface but is not the PCI connection took the computer data exportation, [ 3> was solves the airplane group to interlock the link bottleneck question to make the beneficial attempt. The light interlocks connection card structure like chart 4 to show, it has the standard the DIMM slot connection, the entire control logic, the DDR interface module, and/the string transformation mechanism (RocketIO), all designs in the FPGA chip completes.
May realize between two computers DDR memory interface through it 64, the 200MHz data transmission, the chain 路单 channel maximum actual speed achieves 2Gbit/s, fully used the light to interlock the link performance superiority, has promoted the overall communication performance.

Chart 4 the light interlocks the connection card structure
Under introduced applies RocketIO to the light interlocks in the connection card design process.
In the design has chosen the Custom prototype, it contained in the RocketIO module all attributes, the user has been allowed according to need to choose the corresponding attribute and the formulation user agreement. Through the establishment attribute "TX_DATA_WIDTH" is 4, may permit 32 bit parallel data the input. The data carries on the transmission by the frame way, transmission frame form like chart 5 shows:

Chart 5 transmission frame form
Establishes the clock to revise the sequence and the length, as follows shows:
CLK_COR_SEQ_1_1 is 00.1101111 billion
CLK_COR_SEQ_1_2 is 00.010010101 billion
CLK_COR_SEQ_1_3 is 00.010110101 billion
CLK_COR_SEQ_1_4 is 00.010110101 billion
CLK_COR_SEQ_LEN is 4
Therefore, in front of frame joins the clock to revise the character "BC95B5B5".
Establishes the CRC verification the head (SOP), the tail (EOP) and the verification pattern, as follows shows:
CRC_END_OF_PKT is "K29_7"
CRC_FORMAT is "USER_MODE"
CRC_START_OF_PKT is "K27_7"
Data frame calling order as follows:
...
...
Case (txstate)
3'b000: Begin
Sel<= 1'b0;
Txstate <= 3'b001;
Txaddr <= 0; //RAM地址信号
Su_cnt <= 0;
Data_36 <= 0;
End
3'b001: Begin
Sel <= 1'b0;
If (su_cnt < 10) //连续发�80�?“BC95B5B5�?BR> Begin
Txaddr <= txaddr+1;
If (txaddr == 7)
Begin
Txaddr <= 0;
Txstate <= 3'b001;
End
End
Else
Begin
Sel <= 1'b0;
Txaddr <= 8;//帧头地址
Txstate <= 3'b010;
End
Su_cnt <= su_cnt + 1'b1;
End
3'b010: Begin
Txstate <= 3'b011;
Txaddr <= 9; //帧尾地址
End
3'b011: Begin
Sel <= 1'b1;
Data <= data + 1;//发�的数�?BR>If (data==2048)
Begin
Txstate <= 3'b000;
Sel <= 1'b0;
End
End
Default: Begin
Txstate <= 3'b000;
Txaddr <= 0;
Su_cnt <= 0;
End
Endcase
...
...
The revision character, CRC verify EOP, SOP all is deposits in RAM the data, in transmission data time according to needs to put in them around the data to compose the transmission frame. "Sel" = 0 choices transmits in RAM the data, "Sel" = 1 choice transmission counter idea value.
In the receiving end, through judges EOP, the SOP limits data scope, thus stores the data to double port RAM in.
4 concluding remark
At present, each kind of application logarithm according to transmissibility request more and more high, is high speed serially interlocks the technology because carries on the clock and the data merge the transmission, thus has overcome in the high speed parallel data transmission process clock and the data vibration question. Xilinx Corporation's Virtex- II Pro in the FPGA component provides uses in the realization high speed serial to interlock RocketIO the IP nucleus to have the use simply, the disposition is nimble, the integration rate higher merit, we use in it to solve the light to interlock in the connection card the high speed serial data transmission sdt question, simplified the design, enhanced the system integration rate and the reliability. At the same time, in based on ground the auspicious company on the labor controlling machine motherboard we to complete the light to interlock the connection card feasible test.

Reference
[ 1> grandson navigation Xilinx programmable logic component high-level application and design skill Beijing: Electronics industry publishing house, 2,004
[ 2> RocketIOTM Transceiver User Guide.October 16, 2,002
[ The 3> well literary talent, Tian Jingdong, open dies for, Liu health, week leather, Zhang Yimo
Uses in the airplane group system high speed light interconnecting network connection card design [ J>. photoelectron ∙ Laser, 2,000
[ 4> Xia Yuwen Designs from the algorithm to the hardware logic realization
Higher education publishing house, 2,001

Author synopsis
The fence is brave, the Beijing scientific and technical university information engineering institute is reading the postgraduate candidate. The research interest is the instrument measuring appliance design and the application, inserts the type system and so on. The present research direction is the high speed figure design and the high speed PCB design and the application.